Field of the Disclosure
This disclosure pertains in general to phase locked loops (PLLs) and more particularly to a sample and reset type-I PLL.
Description of the Related Art
PLLs are widely employed in radio, telecommunications, computers, and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete PLL functionality, PLLs are widely used in modern electronic devices, with output frequencies ranging from a few hertz up to many gigahertz.
PLLs can be implemented as either a type-I PLL or a type-II PLL. Type-II PLL typically uses a large capacitor for improving stability of the loop, which increases the die cost and also causes leakage current issues as the technology scales down to deep sub-micron CMOS process technologies. A type-I PLL can reduce leakage current issues by implementing a linear phase detection and also by eliminating the large capacitor for stability. A drawback of conventional type-I PLLs is sub-harmonic locking, where the type-I PLL locks the loop to a frequency of the divider clock signal that is a sub-harmonic value of a frequency of an oscillator output signal of a voltage-controlled oscillator (VCO). Conventional type-I PLLs use a separate frequency detector loop that prevents the PLL from sub-harmonic locking by ensuring that the VCO oscillates at the proper frequency.